We are proud to announce the birth of the Free Silicon Foundation (https://f-si.org)!
We organize a conference in Paris, March 14-16 2019, to promote:
1. Free and Open Source (FOS) CAD tools for designing #VLSI circuits
2. the sharing of hardware designs
3. common standards
4. the freedom of users in the context of #silicon technology
Program and submissions:
https://wiki.f-si.org/index.php/FSiC2019
@fsi I'm glad you exist, we need trustworthy FOSH computation.
Are there recordings of the first conference?
Also: Localized RISCV fabbing when? 
@phryk
Thank you!
Last year's conference was a smaller event (one day only) and the slides are available here:
https://www-soc.lip6.fr/events/pastevents/2018/ . For this year, recordings are not planned yet.
We contacted foundries too - let's see how far we can go in the direction of opening the PDKs: We have already fabricated RISCV chips, but various NDAs did not allow to publish layouts. We are working to change that. At FSiC there will be a session about this too.
It depends from the foundry. Still, 100% self-created standard cells do not contain (if at all) accurate spice models necessary to make analog components (needed for example for input/output) so only simple digital-only circuits are possible.
If the self-created cells can be derived from general abstract principles (and then adapted to the exact foundry parameters), the foundry should not be able to claim any ownership.
@fsi
So for every foundry, to 'free' the library incl. the simulation models, you have to repeat the foundries work of producing a test circuit, characterize it and then derive models from it.
That's hell of a task.
Hope they cooperate instead and give the data voluntarily.
@fsi
Do foundries limit you in using self-created PDKs for basic elements?
Do they claim ownership of self created layouts when their design rules and layer definitions are used?