Is it possible to design a silicon chip using 100% Free and Open Source (FOS) tools?
Can one publish the layout?
Which impact can be expected?

These are few of the questions that thirty-six speakers will address at the second Free Silicon Conference ().

Last chance to attend: reservation deadline is next week (February 21):
wiki.f-si.org/index.php/FSiC20

Cannot join in Paris? No worries! We are preparing the equipment to record all the sessions.

Tomorrow (Sunday February 3) the "CAD and Open Hardware" conference will take place at (Brussels):

fosdem.org/2019/schedule/track

Last year's edition (with video-recordings):
archive.fosdem.org/2018/schedu

Twenty-seven speakers have already confirmed their presence at the Free Silicon Conference ():

wiki.f-si.org/index.php/FSiC20

The high-level design session will include speakers from:

1. Gaut (gaut.fr/)
2. GHDL (ghdl.free.fr/)
3. SpinalHDL (github.com/SpinalHDL)

Twenty-five speakers have already confirmed their presence at the Free Silicon Conference ():

wiki.f-si.org/index.php/FSiC20

The introduction on Day 1 will begin with talks of:

1. Purism (puri.sm/)
2. Wiring (wiring.org.co/)
3. Echopen (echopen.org/)

Which impact will the first free and open (layout included) chips have on security, education and cooperative projects?

Do you believe that Free Software should be the default option for publicly financed software? Let’s convince your political representatives! Sign our open letter: publiccode.eu/

youtube.com/watch?v=iuVUzg6x2y

The 35th Chaos Communication Congress, , ended few days ago. All talks can be seen at
media.ccc.de/c/35c3
and browsed by theme:
halfnarp.events.ccc.de/

A small selection about and place-and-route tools:

LibreSilicon - decentralizing semiconductor manufacturing
media.ccc.de/v/35c3-9410-libre

The nextpnr FOSS FPGA place-and-route tool
media.ccc.de/v/35c3-9612-the_n

@mansr

OpenCores is specialized on FPGAs:
opencores.org/maintainers/olis

However, HDL code alone is not sufficient for silicon. It is just one input for the design loops involving place-and-route, parameter-extraction, timing-analysis, etc.

By creating FOS CAD tools we are bridging the gap between HDL and layouts.

@kmicu

Not all CAD tool vendors publish part or all of their licenses, hence the list below is not exhaustive:
synopsys.com/verification/prot (section 2.2 comma 3)
s3.mentor.com/company/enduser- (section 4.1)

Those using such tools should refer to the text of their licenses directly.

Where can you download, modify and share a silicon IP block just like you do, say, with gcc?

Nowhere.

The licenses of mainstream proprietary silicon CAD tools explicitly forbid publishing anything created with them. This is partially due to keep algorithms, such as place-and-route, more secret.

It is like writing a book with a proprietary word processor and then not having permission to publish it for not revealing how the grammar checker works.

Free silicon requires free CAD tools.

@balu

Totally agree.

In HiFive/SiFive just a small portion of the source/documentation is open, and it is not free (no copyleft license). Nor are the tools to generate the layout.

We want to change that - see the conference program: wiki.f-si.org/index.php/FSiC20

@stman @maiki

Merci!

We will soon put on the wiki the answers to your question and to the many more we are receiving.

@bobstechsite @codesections @fsfe

Our logo is probably more similar to the one of the fsf than to the one of the fsfe.

We are not affiliated with any entity, but we are certainly aligned with both fsf and fsfe and we had personal discussions with both.

We know fossi as well.

@ente@chaos.social @phryk

Thanks for the suggestion. In case of need we'll come back to you. For now we have several other logistic aspects to focus on first.

@Chaos_99

It depends from the foundry. Still, 100% self-created standard cells do not contain (if at all) accurate spice models necessary to make analog components (needed for example for input/output) so only simple digital-only circuits are possible.

If the self-created cells can be derived from general abstract principles (and then adapted to the exact foundry parameters), the foundry should not be able to claim any ownership.

@maiki

Some members are listed here: wiki.f-si.org/index.php/FSiC20 .

Our logo intentionally resembles the FSF logo because we aim to be for silicon what the FSF is for software. We had extensive discussions with Richard Stallman before deciding to create the F-Si.

The F-Si is formally a "Swiss Verein" according to Art. 60-79 of the ZGB (see en.wikipedia.org for legal details and budget checking rules).

The F-Si budget is currently below 10kEur.

@phryk
Thank you!

Last year's conference was a smaller event (one day only) and the slides are available here:
www-soc.lip6.fr/events/pasteve . For this year, recordings are not planned yet.

We contacted foundries too - let's see how far we can go in the direction of opening the PDKs: We have already fabricated RISCV chips, but various NDAs did not allow to publish layouts. We are working to change that. At FSiC there will be a session about this too.

We are proud to announce the birth of the Free Silicon Foundation (f-si.org)!

We organize a conference in Paris, March 14-16 2019, to promote:

1. Free and Open Source (FOS) CAD tools for designing circuits
2. the sharing of hardware designs
3. common standards
4. the freedom of users in the context of technology

Program and submissions:
wiki.f-si.org/index.php/FSiC20

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