We prepared a white paper for the containing recommendations about as encouraged last November:


Please discuss it or endorse it by replying to this thread.
The paper will be delivered on January 31.

A first draft was shared in December with:

* april.org @aprilorg
* fsfe.org @fsfe
* fsf.org @fsf
* Aral Balkan @aral
* waag.org @waag
* sfconservancy.org @conservancy
* gpl-violations.org
* commonsnetwork.eu

What are the limitations of existing free and open-source (FOS) electronic design automation () tools?

What is it missing to design a chip with 1+ Million gates?

Which will be the first foundry to open a process design kit (PDKs)?

These are some of the questions that will be addressed at the third Free Silicon Conference () which will be held in Zurich on June 4-6 2020.

More info at:

Picture: the Raven chip of Tim Edwards

The third Free Silicon Conference, , will take place in Zurich on June 4-6 2020.

It builds on top of the previous edition (FSiC2019), where 100+ experts and enthusiasts gathered together to discuss how to design free/libre silicon chips.

To get involved visit:

The submission window opens on January 1st and participation is free of charge.

The European Commission is organizing a "Workshop about the future of Open Source Software and Open Source Hardware", Brussels, November 14-15 2019:


Online registration will close on November 6.

Is it possible to simulate transistors using open-source tools only?

How fast are the available solvers?

How hard is it to interface with existing PDKs?

The following talks provide very promising answers:

* ngspice - an open source mixed signal circuit simulator, by Holger Vogt

* Gnu Circuit Analysis Package (GnuCap), by Al Davis

* Converting 45nm transistor netlists to open standards, by Thomas Benz

Which foundries are the most friendly to open-source? Is there an open-source ?

Kholdoun Torki of Circuits-Multi-Projects (mycmp.fr/) provided a great overview:

"Towards Foundry PDKs on Free CAD Tools"

All the recordings of the Free Silicon Conference are now online:


Day 1 focuses on high-level design. Some of the concepts presented in the first talks can be partially applied to FPGAs as well

Day 2 discusses aspects closer to silicon, such as PDKs, memory generators and layouting

Day 3 presents hands-on tutorials

The full program is available at:

The past Free Silicon Conference was opened with a great talk by Todd Weaver from :

"The Future of Computing and Why You Should Care"


We proudly announce to run our own instance to host the videos of the past Free Silicon Conference 2019:


Is it possible to design a silicon chip using 100% Free and Open Source (FOS) tools?
Can one publish the layout?
Which impact can be expected?

These are few of the questions that thirty-six speakers will address at the second Free Silicon Conference ().

Last chance to attend: reservation deadline is next week (February 21):

Cannot join in Paris? No worries! We are preparing the equipment to record all the sessions.

Tomorrow (Sunday February 3) the "CAD and Open Hardware" conference will take place at (Brussels):


Last year's edition (with video-recordings):

Twenty-seven speakers have already confirmed their presence at the Free Silicon Conference ():


The high-level design session will include speakers from:

1. Gaut (gaut.fr/)
2. GHDL (ghdl.free.fr/)
3. SpinalHDL (github.com/SpinalHDL)

Twenty-five speakers have already confirmed their presence at the Free Silicon Conference ():


The introduction on Day 1 will begin with talks of:

1. Purism (puri.sm/)
2. Wiring (wiring.org.co/)
3. Echopen (echopen.org/)

Which impact will the first free and open (layout included) chips have on security, education and cooperative projects?

Do you believe that Free Software should be the default option for publicly financed software? Let’s convince your political representatives! Sign our open letter: publiccode.eu/


The 35th Chaos Communication Congress, , ended few days ago. All talks can be seen at
and browsed by theme:

A small selection about and place-and-route tools:

LibreSilicon - decentralizing semiconductor manufacturing

The nextpnr FOSS FPGA place-and-route tool


OpenCores is specialized on FPGAs:

However, HDL code alone is not sufficient for silicon. It is just one input for the design loops involving place-and-route, parameter-extraction, timing-analysis, etc.

By creating FOS CAD tools we are bridging the gap between HDL and layouts.


Not all CAD tool vendors publish part or all of their licenses, hence the list below is not exhaustive:
synopsys.com/verification/prot (section 2.2 comma 3)
s3.mentor.com/company/enduser- (section 4.1)

Those using such tools should refer to the text of their licenses directly.

Where can you download, modify and share a silicon IP block just like you do, say, with gcc?


The licenses of mainstream proprietary silicon CAD tools explicitly forbid publishing anything created with them. This is partially due to keep algorithms, such as place-and-route, more secret.

It is like writing a book with a proprietary word processor and then not having permission to publish it for not revealing how the grammar checker works.

Free silicon requires free CAD tools.


Totally agree.

In HiFive/SiFive just a small portion of the source/documentation is open, and it is not free (no copyleft license). Nor are the tools to generate the layout.

We want to change that - see the conference program: wiki.f-si.org/index.php/FSiC20

Show more

mastodon.f-si.org is one server in the network