Is it possible to simulate transistors using open-source tools only?
How fast are the available solvers?
How hard is it to interface with existing PDKs?
The following talks provide very promising answers:
* ngspice - an open source mixed signal circuit simulator, by Holger Vogt
* Gnu Circuit Analysis Package (GnuCap), by Al Davis
* Converting 45nm transistor netlists to open standards, by Thomas Benz
Which foundries are the most friendly to open-source? Is there an open-source #PDK?
Kholdoun Torki of Circuits-Multi-Projects (https://mycmp.fr/) provided a great overview:
"Towards Foundry PDKs on Free CAD Tools"
All the recordings of the Free Silicon Conference are now online:
Day 1 focuses on high-level design. Some of the concepts presented in the first talks can be partially applied to FPGAs as well
Day 2 discusses aspects closer to silicon, such as PDKs, memory generators and layouting
Day 3 presents hands-on tutorials
The full program is available at:
The past Free Silicon Conference was opened with a great talk by Todd Weaver from #Purism:
"The Future of Computing and Why You Should Care"
Is it possible to design a silicon chip using 100% Free and Open Source (FOS) tools?
Can one publish the layout?
Which impact can be expected?
These are few of the questions that thirty-six speakers will address at the second Free Silicon Conference (#FSiC).
Last chance to attend: reservation deadline is next week (February 21):
Cannot join in Paris? No worries! We are preparing the equipment to record all the sessions.
Tomorrow (Sunday February 3) the "CAD and Open Hardware" conference will take place at #FOSDEM (Brussels):
Last year's edition (with video-recordings):
Twenty-seven speakers have already confirmed their presence at the Free Silicon Conference (#FSiC):
The high-level design session will include speakers from:
Twenty-five speakers have already confirmed their presence at the Free Silicon Conference (#FSiC):
The introduction on Day 1 will begin with talks of:
Which impact will the first free and open (layout included) chips have on security, education and cooperative projects?
A small selection about #silicon and place-and-route tools:
LibreSilicon - decentralizing semiconductor manufacturing
The nextpnr FOSS FPGA place-and-route tool
OpenCores is specialized on FPGAs:
However, HDL code alone is not sufficient for silicon. It is just one input for the design loops involving place-and-route, parameter-extraction, timing-analysis, etc.
By creating FOS CAD tools we are bridging the gap between HDL and layouts.
Not all CAD tool vendors publish part or all of their licenses, hence the list below is not exhaustive:
https://www.synopsys.com/verification/prototyping/haps/synopsys-license-agreement.html (section 2.2 comma 3)
http://s3.mentor.com/company/enduser-english.pdf (section 4.1)
Those using such tools should refer to the text of their licenses directly.
Where can you download, modify and share a silicon IP block just like you do, say, with gcc?
The licenses of mainstream proprietary silicon CAD tools explicitly forbid publishing anything created with them. This is partially due to keep algorithms, such as place-and-route, more secret.
It is like writing a book with a proprietary word processor and then not having permission to publish it for not revealing how the grammar checker works.
Free silicon requires free CAD tools.
Thanks for the suggestion. In case of need we'll come back to you. For now we have several other logistic aspects to focus on first.
It depends from the foundry. Still, 100% self-created standard cells do not contain (if at all) accurate spice models necessary to make analog components (needed for example for input/output) so only simple digital-only circuits are possible.
If the self-created cells can be derived from general abstract principles (and then adapted to the exact foundry parameters), the foundry should not be able to claim any ownership.
Some members are listed here: https://wiki.f-si.org/index.php/FSiC2019#Organizing_committee .
Our logo intentionally resembles the FSF logo because we aim to be for silicon what the FSF is for software. We had extensive discussions with Richard Stallman before deciding to create the F-Si.
The F-Si is formally a "Swiss Verein" according to Art. 60-79 of the ZGB (see en.wikipedia.org for legal details and budget checking rules).
The F-Si budget is currently below 10kEur.