Is it possible to design a silicon chip using 100% Free and Open Source (FOS) tools?
Can one publish the layout?
Which impact can be expected?

These are few of the questions that thirty-six speakers will address at the second Free Silicon Conference ().

Last chance to attend: reservation deadline is next week (February 21):
wiki.f-si.org/index.php/FSiC20

Cannot join in Paris? No worries! We are preparing the equipment to record all the sessions.

The 35th Chaos Communication Congress, , ended few days ago. All talks can be seen at
media.ccc.de/c/35c3
and browsed by theme:
halfnarp.events.ccc.de/

A small selection about and place-and-route tools:

LibreSilicon - decentralizing semiconductor manufacturing
media.ccc.de/v/35c3-9410-libre

The nextpnr FOSS FPGA place-and-route tool
media.ccc.de/v/35c3-9612-the_n

Where can you download, modify and share a silicon IP block just like you do, say, with gcc?

Nowhere.

The licenses of mainstream proprietary silicon CAD tools explicitly forbid publishing anything created with them. This is partially due to keep algorithms, such as place-and-route, more secret.

It is like writing a book with a proprietary word processor and then not having permission to publish it for not revealing how the grammar checker works.

Free silicon requires free CAD tools.

We are proud to announce the birth of the Free Silicon Foundation (f-si.org)!

We organize a conference in Paris, March 14-16 2019, to promote:

1. Free and Open Source (FOS) CAD tools for designing circuits
2. the sharing of hardware designs
3. common standards
4. the freedom of users in the context of technology

Program and submissions:
wiki.f-si.org/index.php/FSiC20

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