The third Free Conference () has been postponed to 2021
because of the coronavirus pandemic.

Watch the teaser for FSiC2021!

We prepared a white paper for the containing recommendations about as encouraged last November:

Please discuss it or endorse it by replying to this thread.
The paper will be delivered on January 31.

A first draft was shared in December with:

* @aprilorg
* @fsfe
* @fsf
* Aral Balkan @aral
* @waag
* @conservancy

What are the limitations of existing free and open-source (FOS) electronic design automation () tools?

What is it missing to design a chip with 1+ Million gates?

Which will be the first foundry to open a process design kit (PDKs)?

These are some of the questions that will be addressed at the third Free Silicon Conference () which will be held in Zurich on June 4-6 2020.

More info at:

Picture: the Raven chip of Tim Edwards

The third Free Silicon Conference, , will take place in Zurich on June 4-6 2020.

It builds on top of the previous edition (FSiC2019), where 100+ experts and enthusiasts gathered together to discuss how to design free/libre silicon chips.

To get involved visit:

The submission window opens on January 1st and participation is free of charge.

Is it possible to simulate transistors using open-source tools only?

How fast are the available solvers?

How hard is it to interface with existing PDKs?

The following talks provide very promising answers:

* ngspice - an open source mixed signal circuit simulator, by Holger Vogt

* Gnu Circuit Analysis Package (GnuCap), by Al Davis

* Converting 45nm transistor netlists to open standards, by Thomas Benz

Which foundries are the most friendly to open-source? Is there an open-source ?

Kholdoun Torki of Circuits-Multi-Projects ( provided a great overview:

"Towards Foundry PDKs on Free CAD Tools"

All the recordings of the Free Silicon Conference are now online:

Day 1 focuses on high-level design. Some of the concepts presented in the first talks can be partially applied to FPGAs as well

Day 2 discusses aspects closer to silicon, such as PDKs, memory generators and layouting

Day 3 presents hands-on tutorials

The full program is available at:

The past Free Silicon Conference was opened with a great talk by Todd Weaver from :

"The Future of Computing and Why You Should Care"

Is it possible to design a silicon chip using 100% Free and Open Source (FOS) tools?
Can one publish the layout?
Which impact can be expected?

These are few of the questions that thirty-six speakers will address at the second Free Silicon Conference ().

Last chance to attend: reservation deadline is next week (February 21):

Cannot join in Paris? No worries! We are preparing the equipment to record all the sessions.

The 35th Chaos Communication Congress, , ended few days ago. All talks can be seen at
and browsed by theme:

A small selection about and place-and-route tools:

LibreSilicon - decentralizing semiconductor manufacturing

The nextpnr FOSS FPGA place-and-route tool

Where can you download, modify and share a silicon IP block just like you do, say, with gcc?


The licenses of mainstream proprietary silicon CAD tools explicitly forbid publishing anything created with them. This is partially due to keep algorithms, such as place-and-route, more secret.

It is like writing a book with a proprietary word processor and then not having permission to publish it for not revealing how the grammar checker works.

Free silicon requires free CAD tools.

We are proud to announce the birth of the Free Silicon Foundation (!

We organize a conference in Paris, March 14-16 2019, to promote:

1. Free and Open Source (FOS) CAD tools for designing circuits
2. the sharing of hardware designs
3. common standards
4. the freedom of users in the context of technology

Program and submissions:

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