The call for Design Enablement Teams () opened on 4 June. The deadline is on 30 July 2025 (soon!).

A DET provides support for designing chips. This includes application engineering support, cloud-based EDA infrastructure, setup of design environment, foundry access, supply chain management: chips-ju.europa.eu/Appendix6_I (page 10)

Call details: chips-ju.europa.eu/CallDetails

Past workshop: chips-ju.europa.eu/Events-deta

See also slide 12 of: wiki.f-si.org/index.php?title=

Xueyan Zhao announced that is expected to open a 55nm PDK in July 2025:

* ICSprout is jointly established by Zhejiang Provincial Government and Zhejiang University
* It has 12-inch CMOS 180/55nm process lines
* First test chip on ICSprout 55nm Open PDK taped-out in June 15 2025
* Price range: 1400$ - 5600$/mm2

For more information see slide 16 of wiki.f-si.org/index.php?title=

The 2025 Free Silicon Conference is over. Slides are online, videos will follow.

Highlights:
* China to open a 55nm PDK in weeks
* ChipsJU DET call is open
* DE:SIGN + Taiwan partnership (submit pre-proposals by 1 October)
* Progress on parasitic extraction
* Former CTO of Studio (Peter Thoma) spoke at FSiC
* ElemRV: Open-source microcontroller taped in IHP130
* Visualization of chips in action: znah.net/tt09/

FSiC2025 is fully booked.

120+ engineers, hackers, and researchers will gather in Frankfurt an der Oder to discuss libre EDA, PDKs, on-going projects and more.

Check the program at:
wiki.f-si.org/index.php/FSiC20

Video recordings will be published after the conference.

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