Free Silicon Foundation @fsi@mastodon.f-si.org

The #ChipsJU call for Design Enablement Teams (#DET) opened on 4 June. The deadline is on 30 July 2025 (soon!).

A DET provides support for designing chips. This includes application engineering support, cloud-based EDA infrastructure, setup of design environment, foundry access, supply chain management: https://www.chips-ju.europa.eu/Appendix6_I.pdf (page 10)

Call details: https://www.chips-ju.europa.eu/CallDetails/?id=c604c14f-6f1f-f011-9989-000d3ab0a56e

Past workshop: https://www.chips-ju.europa.eu/Events-detail/?id=61668f10-180b-f011-bae2-000d3ab909f8

See also slide 12 of: https://wiki.f-si.org/index.php?title=One_year_of_experience_with_IHP_OpenMPW_shuttles:_a_review

Are you working in Germany? Are interested to cooperate with Taiwan for developing open-source EDA?

Then apply by 1 October 2025 for pre-proposals:

https://wiki.f-si.org/index.php?title=Update_on_German_Microelectronics_Design_Initiative

https://www.elektronikforschung.de/foerderung/bekanntmachungen/foerderaufruf-2025-deutschland-taiwan

#Taiwan #Silicon #FOSS #FSiC

Xueyan Zhao announced that #ICSprout is expected to open a 55nm PDK in July 2025:

* ICSprout is jointly established by Zhejiang Provincial Government and Zhejiang University
* It has 12-inch CMOS 180/55nm process lines
* First test chip on ICSprout 55nm Open PDK taped-out in June 15 2025
* Price range: 1400$ - 5600$/mm2

For more information see slide 16 of https://wiki.f-si.org/index.php?title=Making_Open_Silicon_Design_Everywhere:_Using_Cloud-based_Open_Agile_EDA_Platform

#OpenHardware #FSiC #Silicon #FOSS #NGIZero #IHP